The multi-chip module Raphael contains one CCD for the 6-core and 8-core SKUs and two CCDs for the 12-core and 16-core SKUs. The new 6 nm cIOD measures 124.7 mm2, which is somewhat larger than the Ryzen 5000 series' 124.9 mm2 cIOD. Aside from DDR5 memory controllers and a PCI-Express Gen 5 root complex, this cIOD includes an iGPU based on the RDNA2 graphics architecture. Certain power-management capabilities from the Ryzen 6000 "Rembrandt" processors are also included.
Amd transistor size series#
It's manufactured on the 6 nm (TSMC N6) node, which is a significant improvement over the GlobalFoundries 12 nm node used for the cIOD of Ryzen 5000 series processors.
The "Zen 4" CCD has 6.57 billion transistors, a 58 percent increase over the "Zen 3" CCD's 4.15 billion transistors.The cIOD (client I/O die) is seeing a lot of innovation. The CCD is 70 mm2 in size, unlike the 83 mm2 Zen 3"CCD. Because of the transition to 5 nm, the Zen 4 CCD is slightly smaller than the Zen 3 CCD despite having more transistors (TSMC N5 process). The size of the L1 branch target buffer (BTB) has been raised from 1 KB to 1.5 KB. The dispatch stage's reorder buffer (ROB) has been increased from 256 to 320 entries. The shared 元 cache's latency has also increased, from 46 to 50 cycles. The expansion of the L2 cache increased latency somewhat, from 12 to 14. The L1I and L1D caches remain 32 KB each, whereas the L2 cache has more than doubled in size. AMD's Mark Papermaster announced at the Ryzen 7000 launch event that the company has increased the core's micro-op cache from 4 K entries to 6.75 K entries. Chiakokhua (aka Retired Engineer) posted a table comparing the latencies of the various caches to those of the "Zen 3" core.
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